37 / 63 · Concept

Serial inputs and frame boundaries

Define input order and valid edges, then calculate bit placement in serial-to-parallel conversion.

Turn time order into vector positions

A serial input supplies one bit at each accepted edge. Applying q<={q[1:0],din} to a three-bit register^{Register A circuit that stores multiple bits of state. The synchronous registers in this course store their specified inputs at a clock edge. Learn more} initially at q=000 and receiving 1,0,1,1 gives

Accepted bit count	din	Updated q
1	1	001
2	0	010
3	1	101
4	1	011

The new bit enters on the right and existing bits move to higher indices. The register is a sliding window of the latest three bits; accepting the fourth discards the first.

Each column below records one rising edge^{Rising edge The instant at which the clock changes from 0 to 1. Distinguish it from a level, which refers to the entire interval during which CLK=1. Learn more}. Inputs are pre-edge; states labeled “after” are post-update. Alignment is sample order, not physical propagation delay^{Propagation delay The time from an input change until the output settles to the correct value. Logical equivalence and timing behavior are separate properties. Learn more}. The first column resets. Of the following accepted bits 1,0,1,1, only the latest three remain in q. Watch the first bit leave in the last column.

From serial input to parallel state

View waveform data

Wave data: each character is one interval; a dot holds the previous state; p is a clock cycle.
Signal	Wave	Bus values
edge	`23452`	E0 → E1 → E2 → E3 → E4
reset	`10...`
din	`0101.`
q after	`23452`	000 → 001 → 010 → 101 → 011

MSB-first and LSB-first are communication rules

Sending an eight-bit value MSB^{MSB The bit with the highest place value. Its index depends on the vector's declaration direction, so do not assume it always has the largest index. Learn more} first and receiving its eight bits in this way reconstructs the original vector. Sending LSB^{LSB The bit with the lowest place value. Check both the notation direction and the indexing rules. Learn more} first reverses its placement, requiring the shift direction or final rearrangement to change. This is a protocol agreed by sender and receiver, not merely a display option.

Data values alone do not define a frame

State must identify the first bit, the number of bits accepted and when the result can be consumed. A counter of accepted bits commonly accompanies valid or done. If input pauses, count accepted data items, not clocks.

accept_k=valid_k\land ready_k

With a ready/valid^{Handshake A contract that accepts a transfer when the sender's valid and the receiver's ready are both 1 at the same edge. It also defines how data must be held while waiting. Learn more} interface, update both the shift state and count only at edges where this condition is true. Enabling only one misaligns data and length. The provided continuous-input lab is the simple case that accepts every data edge.

Try it yourself

In an eight-bit frame, valid is 0 for two cycles after the fourth bit. With ready=1, what should the receive counter and shift register do?

Read the explanation

accept=0 in both cycles, so hold both the counter and data register. The next valid bit is the fifth. Counting clocks alone could incorrectly signal completion before all data arrives.