Digital signals: when voltages represent 0 and 1

What you should be able to build

This course moves briskly through introductory university-level digital logic design and checks each idea with a circuit. High-school algebra is enough to start; basic programming experience helps with the RTL labs. First, connect gates → combinational circuits → storage elements → state machines. The optional advanced chapters then extend these foundations to datapaths and interfaces.

The goal of this lesson is more than memorizing “high voltage means 1.” You should be able to explain over what range, and from what time onward, a correct logic value is guaranteed.

A logic value is an interpretation of a voltage

Logic circuits compute with $0$ and $1$, but wires carry continuously varying voltages. The input specification defines a reading of 0 at or below $V_{IL}$ and 1 at or above $V_{IH}$. Neither interpretation is guaranteed between the two thresholds. The device data sheet specifies the actual permitted voltage range and thresholds.

Consider an educational 3.3 V circuit. The following values are illustrative, not specifications for a particular product.

An input of 1.4 V is not a “third logic value.” It falls outside the conditions under which the digital model guarantees a result. A transition from 0 to 1 passes through this interval, so we must also specify when the output is observed.

The margin between output and input specifications

Assume a maximum low driver output of $V_{OL}=0.2\,\mathrm V$ and a minimum high output of $V_{OH}=2.8\,\mathrm V$. The noise margins^{iNoise margin The margin between a driver's guaranteed output voltage and a receiver's input decision threshold. It is calculated from the difference between static voltage specifications.} are

Even with +0.4 V of noise added to the low output, 0.6 V remains in the low input range. This is a static margin, assuming the voltage specifications and load conditions are met. This number alone does not characterize short pulses or wiring reflections.

Consider function and timing together

An AND gate outputs 1 for inputs 11. That does not guarantee an output of 1 at the very instant the inputs change. Add the maximum gate delays along each path, then use the longest total as the delay bound. For two gates in series with maximum delays of 2 ns and 3 ns, this model allows up to 5 ns after the inputs settle.

Leaving an input unconnected is also different from driving it with 0. In a simulator, X represents an unknown value and Z a high-impedance drive state; neither corresponds one-to-one to a particular physical voltage. The button exercises in this course use a stable 0/1 model.

Further reading: MIT OpenCourseWare — The Digital Abstraction

Lab · Cross a noise-margin boundary

1. Select transmit 0. The output is fixed at its worst-case low voltage, 0.20 V. Set the noise to +0.60 V: the receiver sees 0.80 V, which still guarantees 0.
2. Press the right arrow to add another 10 mV of noise. At 0.81 V, the result changes to “not guaranteed.” That does not mean it immediately becomes 1.
3. For transmit 1, subtract noise from the 2.80 V output. A received 1 is guaranteed through −0.80 V, but not at −0.81 V.
4. A larger disturbance can take the input into the opposite valid region. The receiver may then classify it as a valid logic level even though the transmitted data is wrong. Valid voltage and correct data are separate conditions.

Inputs outside the lab's 0–VDD range are not clamped into a valid region. Check the actual device's permitted input range, clamp current and transient-pulse conditions separately in its data sheet. This exercise does not predict damage or the dynamic response of a particular device.