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Shift-circuit verification and data/valid alignment
Find errors hidden by symmetric patterns and one-cycle misalignment of validity signals.
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Choose patterns that expose errors
Shifting only 0000 or 1111 can hide reversed direction. Track positions using an asymmetric pattern such as 1000 or a single 1. Always starting from all zeros can also miss some initialization-path and hold faults.
For a three-bit registerRegister A circuit that stores multiple bits of state. The synchronous registers in this course store their specified inputs at a clock edge. Learn more starting at 000, inputs 1,0,0 yield 001→010→100. A reverse-direction implementation yields 100→010→001 and differs from the first edge.
Review the reference model in two forms
Compare this arithmetic model with actual sliceSlice An operation selecting a contiguous range of bits from a vector. The selected range determines the result width and bit order. Learn more/concatenation RTL at every accepted edge. For N=3, eight states and two inputs give 16 transitions that can be checked exhaustively. Add reset and enable combinations separately.
Each column below records a rising edgeRising edge The instant at which the clock changes from 0 to 1. Distinguish it from a level, which refers to the entire interval during which CLK=1. Learn more. Inputs are pre-edge; states labeled “after” are post-update. Alignment shows sampling order, not physical propagation delayPropagation delay The time from an input change until the output settles to the correct value. Logical equivalence and timing behavior are separate properties. Learn more. Initially q=000. At the second edge enable=0, so q stays 001 even though din changes. Count clock edges and accepted inputs separately.
View waveform data
| Signal | Wave | Bus values |
|---|---|---|
| edge | 2345 | E0 → E1 → E2 → E3 |
| enable | 101. | |
| din | 10.1 | |
| q after | 2.34 | 001 → 010 → 101 |
Reproduce the waveform: advance once with din=1 to obtain 001. Advance with enable=0, din=0 and retain 001. Re-enable and apply din=0,1 to obtain 010,101. This model handles only the data register; the next section separately examines why valid must stall with the same enable.
Synchronous reset takes priority over enable. With enable=0, hold the stored value. q=000; q_next = (2q + din) mod 8
Valid is part of the datapath too
If data stalls while valid advances, or data advances while valid stalls, the output consumer can accept the wrong sample. Verifying only that “the output bits are correct” is insufficient to establish a correct interface.
| Test | Expected behavior |
|---|---|
| Continuous normal input | Correct bit order and fixed valid latency |
| enable=0 in the middle | Data and valid hold together |
| Reset in the middle | Valid state from the previous frame is cleared |
| Consecutive new frames | Distinguish the old frame's end from the new frame's start |
Record the accepted-input number during failure analysis to avoid confusing it with the physical clock number. A minimal counterexample containing the frame boundary is more effective than repeatedly inspecting a long waveform.
Try it yourself
Data registers shift only when enable=1, but the valid delay line shifts every clock. Which input most easily exposes the error?
Read the explanation
Insert a stalled edge with enable=0 between two distinct data items. Valid then arrives early or labels the wrong data. Compare against a reference model that applies the same acceptance condition to data and metadata.