22 / 63 · Concept

Synchronous state transitions and the role of the clock

Interpret a synchronous system as registers that all read the same previous state.

The entire state updates together at one edge

For a synchronous circuit with state vector $Q_k$ and input $X_k$ , the central specification is

Q_{k+1}=F(Q_k,X_k),\qquad Y_k=G(Q_k,X_k)

F is the next-state function and G the output function. The clock does not determine what to compute; it determines when the computed next state is stored. Think of all registers^{Register A circuit that stores multiple bits of state. The synchronous registers in this course store their specified inputs at a clock edge. Learn more} as deriving their next values from the same previous state.

Q passes through combinational function F to produce the next-state input. The stored result returns as Q in the following interval, separating calculation between edges from storage at an edge.

Compute next state from previous state

Current state Q: Held between clock edges
F(Q, X): Compute from inputs and previous state
Store at the edge: The computed result becomes the next Q

The clock period must accommodate the slowest path

It takes time for new data to emerge from the source register and to pass through combinational logic to the destination register. Enough setup^{Setup The minimum time that input data must be stable before the capturing clock edge. If it is violated, the stored result is not guaranteed. Learn more} time must remain before the next edge. Short source code does not imply a high achievable clock frequency.

A clock period of 10 ns corresponds to 100 MHz.

f=\frac{1}{T}

Do not skip unit conversion. The reciprocal of 1 ns is 1 GHz; that of 1 ps is 1 THz. A simulation's specified period schedules inputs; it is not a measurement showing that the physical circuit operates at that frequency.

Interpret signals between edges

A register output retains its logical state until the next active edge, while combinational outputs can change between edges. Exceptions depend on whether reset^{Reset A control that returns state to a specified initial value. Define whether it is synchronous or asynchronous and whether it has priority over other controls. Learn more} is synchronous or asynchronous. The provided labs use a single clock and synchronous reset.

Specify input validity, state-update timing and output-observation timing before reading waveforms. A state equation is more accurate than a software-style interpretation that “one line of code executes per clock.”

Try it yourself

What is the period of a 200 MHz clock? If two registers on the same clock use a<=d; b<=a;, does b receive the a updated at that edge?

Read the explanation

The period is 5 ns. b receives a from just before the edge. Both registers compute their next values from the same previous state, so a new d does not traverse both stages in one edge.