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DEMUX and decoder: routing data to a selected path

Compare the direction and roles of MUX, DEMUX and decoder, and verify one-hot and one-hot-or-zero conditions.

A MUX gathers; a DEMUX distributes

A MUX^{Multiplexer A combinational circuit that connects one of several inputs to the output according to a select signal. Specify how select bits map to input numbers. Learn more} forwards one of several data inputs to its output. A DEMUX^{DEMUX A circuit that sends one data input to the output designated by a select signal. The values of unselected outputs must also be specified.} forwards one data input d to a selected output and sets the other outputs to 0. For a 1-to-4 DEMUX with select address $s_1s_0$ ,

y_0=d\overline{s_1}\overline{s_0},\quad y_1=d\overline{s_1}s_0,\quad y_2=ds_1\overline{s_0},\quad y_3=ds_1s_0

See the same function in an enabled decoder

In the diagram below, read a1 and a0 as the select address and enable as data d. Output names d0–d3 correspond to y0–y3 in the equations. The same combinational function can have different names in different contexts.

Interpret enable as data to obtain a DEMUX

d[i] = enable AND (2 × a1 + a0 = i)

With address 10 and data 1, only y2 is 1. With data 0, every output, including the selected one, is 0. Therefore, “exactly one output is always 1” is not the correct one-hot^{One-hot A representation with exactly one bit set to 1. A condition that also permits all zeros is called one-hot-or-zero. Learn more} condition. The full behavior is one-hot-or-zero: at most one output is 1.

Distinguish a select line from an actual write event

To write one of four registers^{Register A circuit that stores multiple bits of state. The synchronous registers in this course store their specified inputs at a clock edge. Learn more}, use write_en as d and the address as the selection. The decoder^{Decoder A circuit that activates the output line corresponding to a binary code. With an enable input, all outputs can be set to 0 when disabled. Learn more} itself stores nothing. A register stores data when it samples its write enable and data at a clock edge. Changing a combinational select line does not immediately change stored data.

Selection and storage are two steps

Address + write_en: Specify where to write and whether to write
Decoder: Generate enable for the selected register
Clock edge: The selected register stores the data

Check not only the selected output's value but also that all other outputs are 0. Four combinations with d=0 plus four with d=1 give eight tests. This functional check does not guarantee freedom from glitches during address transitions.

Try it yourself

With select address s1s0=01, find y3y2y1y0 for d=1 and d=0. When does an assertion requiring exactly one of four register enables to be active fail?

Read the explanation

The outputs are 0010 and 0000 respectively. No active output is correct when d or write_en is 0. The exactly-one condition applies only when d=1.