23 / 63 · Concept

Combinational selection and registered-output latency

Analyze how registering a MUX result changes its interface and latency.

Why add an output register?

A MUX's^{Multiplexer A combinational circuit that connects one of several inputs to the output according to a select signal. Specify how select bits map to input numbers. Learn more} combinational output can change whenever the select signal or data changes. An output register^{Register A circuit that stores multiple bits of state. The synchronous registers in this course store their specified inputs at a clock edge. Learn more} lets the next stage use a value fixed at a clock boundary, but changes observation timing and latency.

Let $a_k,b_k,s_k$ be inputs ready just before edge k, and $q_{k+1}$ the stored value after that edge:

y_k=\overline{s_k}a_k+s_kb_k,\qquad q_{k+1}=y_k

Whenever discussing latency, define when inputs are presented and outputs observed. In an interface whose inputs and outputs are both register outputs, the number of intervening register stages determines cycle latency.

Draw a short timing table first

Just before edge	a	b	sel	y	q just after edge
1	0	1	0	0	0
2	0	1	1	1	1
3	1	0	1	0	0

If sel changes between edges 1 and 2, y changes first while q holds until edge 2. Comparing q directly with the input change can make correct behavior look like an off-by-one error.

The columns below are ordered observation points, not evenly spaced times. Here a=0 and b=1. Notice the interval after sel changes and before the next edge, during which q holds its value.

The order in which y changes and q follows

View waveform data

Wave data: each character is one interval; a dot holds the previous state; p is a clock cycle.
Signal	Wave	Bus values
event	`23452`	E1 after → sel → 1 → E2 after → sel → 0 → E3 after
sel	`01.0.`
y	`01.0.`
q	`0.1.0`

What a register does not solve

Inputs unstable around the capture edge remain unsafe even with a register. A select signal arriving from another clock domain needs a separate synchronization design before direct use. Nor does the register eliminate every glitch on combinational y. Review whether the interface uses only q or whether another path also uses y.

Try it yourself

Consider an input register → MUX → output register, all on the same clock. At which output-register edge is a new value launched by the input register at edge k normally captured?

Read the explanation

In a normal single-cycle synchronous path, it is captured at edge k+1. At edge k, the output register sees the input register's previous value; the new value passes through clock-to-Q and combinational delay to prepare for the next edge. Do not let a new value pass through both registers instantaneously at one edge.