Design check: latency, alignment and preserving accepted inputs

Fix the reference point for counting latency

A three-bit register^{iRegister A circuit that stores multiple bits of state. The synchronous registers in this course store their specified inputs at a clock edge. Learn more} executes q <= {q[1:0], din} only for valid inputs; valid=0 holds q. Starting from 0 just after reset^{iReset A control that returns state to a specified initial value. Define whether it is synchronous or asynchronous and whether it has priority over other controls. Learn more}, apply (valid,din) = (1,1), (0,0), (1,0), (1,1) at successive rising edges^{iRising edge The instant at which the clock changes from 0 to 1. Distinguish it from a level, which refers to the entire interval during which CLK=1. Learn more}.

There are four clock edges but only three shifts. Check that state tracking agrees with any claim about “cycle latency.”

Each column below records a rising edge. Inputs are pre-edge; states labeled “after” are post-update. Alignment is sample order, not physical propagation delay^{iPropagation delay The time from an input change until the output settles to the correct value. Logical equivalence and timing behavior are separate properties. Learn more}. The diagram expands the given input sequence. The second column has valid=0, so state holds. Do not confuse the number of q updates with the number of clock columns.

Further design question

If the design is extended to a pipeline^{iPipeline A structure that divides computation into register-separated stages and overlaps processing of multiple inputs. Data, valid and control signals must be aligned by stage. Learn more} accepting eight-bit data per input, three data-register stages with only one valid-delay stage are incorrect. Apply the same movement rule to data and valid, or design acceptance and forwarding rules together for a stallable buffer.