Lab: exhaustive MUX testing and registered-output analysis

The circuit and observation conditions

When sel is 0, y equals a; when sel is 1, y equals b. sampled_y stores y at a rising clock edge^{iRising edge The instant at which the clock changes from 0 to 1. Distinguish it from a level, which refers to the entire interval during which CLK=1. Learn more}. Even if inputs change, sampled_y holds until the next rising edge.

Before starting

Prepare a Digital Design Studio Desktop project with permission to run it normally. Save each example as rtl/top.sv in a separate folder.

First make a and b different. Verify y=a for sel=0 and y=b for sel=1, then compare against each row of the input file.

SystemVerilog source

module top (
    input logic clk,
    input logic a,
    input logic b,
    input logic sel,
    output logic y,
    output logic sampled_y
);
    assign y = sel ? b : a;
    // Explicit observation register: y remains purely combinational.
    // The register makes this design eligible for logic-netlist-1 simulation.
    always_ff @(posedge clk) sampled_y <= y;
endmodule

Running the lab

In New analysis, select Two-state single-clock v1. Set Clock port to clk and period to 1000ps. Use the following settings, run Preflight, then Run RTL simulation, and compare results.

Each column below corresponds to one item in the input file. Expected combinational y is 0,0,0,1,1,0,1,1. This diagram predicts the function in input order; it does not include sampled_y update times.

Input stimulus

[
  {
    "inputs": {
      "a": [
        false
      ],
      "b": [
        false
      ],
      "sel": [
        false
      ]
    }
  },
  {
    "inputs": {
      "a": [
        false
      ],
      "b": [
        false
      ],
      "sel": [
        true
      ]
    }
  },
  {
    "inputs": {
      "a": [
        false
      ],
      "b": [
        true
      ],
      "sel": [
        false
      ]
    }
  },
  {
    "inputs": {
      "a": [
        false
      ],
      "b": [
        true
      ],
      "sel": [
        true
      ]
    }
  },
  {
    "inputs": {
      "a": [
        true
      ],
      "b": [
        false
      ],
      "sel": [
        false
      ]
    }
  },
  {
    "inputs": {
      "a": [
        true
      ],
      "b": [
        false
      ],
      "sel": [
        true
      ]
    }
  },
  {
    "inputs": {
      "a": [
        true
      ],
      "b": [
        true
      ],
      "sel": [
        false
      ]
    }
  },
  {
    "inputs": {
      "a": [
        true
      ],
      "b": [
        true
      ],
      "sel": [
        true
      ]
    }
  }
]

Compare results

8 cycles · y=1 · sampled_y=1. At 3000ps, check that y=1 while sampled_y=0.

This lab uses 0/1 single-clock RTL. It does not include a #delay, initial or X/Z testbench. A lesson-completion mark records learning progress; it does not represent an actual simulation result.

Write down predictions first

Before running the simulator, calculate combinational output $y$ for the input sequence yourself. The expected sequence is $0,0,0,1,1,0,1,1$. It covers all eight input combinations and provides stronger evidence than a single correct final value.

The register^{iRegister A circuit that stores multiple bits of state. The synchronous registers in this course store their specified inputs at a clock edge. Learn more} output updates at the rising edge, not when the stimulus changes. Record the combinational output just before the edge separately from the register output just after it.

Here the inputs sampled at edge $k$ define post-edge state $q_{k+1}$. sampled_y is that state. Even when values appear at the same time coordinate, check the event order between applying inputs and updating the register.

Three checks to distinguish the defects

1. Reversed selection: before changing the expression to sel ? a : b, predict which vector first fails. Vectors with $a=b$ cannot detect this error.
2. Confused observation points: explain why comparing sampled_y, rather than y, immediately against the combinational answer makes even a correct circuit appear to fail.
3. Input-independence check: change only the unselected input and confirm that $y$ holds. Changes to the selected input must be reflected in $y$.

For each failure, record input, observation time, expected value and actual value on one line. “The waveform looks wrong” does not distinguish a selection error from a one-cycle delay.

Extension exercise

Widening the data to four bits gives $2^{4+4+1}=512$ combinational inputs. Exhaustive checking is still practical, but begin with 0, the maximum value, 0101, 1010 and walking-one patterns to quickly reveal bit-position errors. Update the settings and input file together with the widened circuit.