Adders and carry propagation

Express a one-bit addition with two result bits

The sum of $a_i,b_i,c_i$ ranges from 0 to 3, requiring a sum bit $s_i$ and a carry $c_{i+1}$ into the next position. The sum bit is 1 for an odd number of 1 inputs; the carry is 1 for at least two.

Define generate as $g_i=a_ib_i$ and propagate as $p_i=a_i\oplus b_i$. Then $c_{i+1}=g_i+p_ic_i$, where $+$ means OR. A half adder is the special case without a carry input: its sum is XOR and its carry is AND.

Change the three inputs and confirm that a+b+cin = sum+2×cout always holds. Carry becomes the next position's input; it does not have the same weight as sum.

How far must the carry travel?

Consider four-bit 1111 + 0001. Bit 0 generates a carry that propagates through the other three positions. The stored sum is 0000 and the final carry is 1. In a ripple-carry structure, higher positions may have to wait for carry from lower positions.

Expanding the equations reveals opportunities to compute carry in parallel. Fast adders combine group propagate and generate terms, but trade area against delay through fan-in, wiring and library cells. An RTL + does not necessarily map to a ripple-carry circuit.

Make the sum width explicit in the design

logic [3:0] a, b, sum;
logic cin, cout;
logic [4:0] wide_sum;
assign wide_sum = {1'b0, a} + {1'b0, b} + {4'b0000, cin};
assign sum = wide_sum[3:0];
assign cout = wide_sum[4];

Five bits are sufficient because the maximum is $15+15+1=31$. Decide first whether only the low-order sum is needed, whether carry feeds another stage, and whether saturation is required. The interactive exercise checks a single full-adder stage's truth table^{iTruth table A table listing every possible input combination and its output. Changes over time are checked separately with waveforms. Learn more}; it does not measure the delay of an actual synthesized circuit.