The ALU and zero, negative, carry and overflow flags

Prerequisites: two's complement^{iTwo's complement A representation of signed integers using fixed-width bit patterns. The n-bit range is −2^(n−1) through 2^(n−1)−1. Learn more}, adders, combinational MUXes^{iMultiplexer A combinational circuit that connects one of several inputs to the output according to a select signal. Specify how select bits map to input numbers. Learn more} and bit-width extension.

An ALU produces both a result and status

An ALU selects the result of an operation and emits status bits needed to interpret it. In this design, inputs $A,B$ and result $R$ are $W$ bits, supporting ADD, SUB, AND, OR and XOR. Arithmetic results are always truncated to their low $W$ bits. The same pattern can be read as unsigned^{iUnsigned A rule for interpreting a bit pattern as a nonnegative integer. The n-bit range is 0 through 2^n−1 and may differ from the signed interpretation of the same bits. Learn more} or two's-complement signed, so carry and overflow are separate outputs. Different signed interpretations do not require two adders.

The flags are $Z=(R=0)$ and $N=R_{W-1}$. Z is a reduction NOR of the entire selected result; N is its most significant bit. N=1 means the stored pattern is negative under signed interpretation. After overflow, that sign may differ from the true infinite-precision result.

Separate carry from overflow

For addition, C is the highest bit of extended sum $T$.

V is 1 when both input signs match but the result sign differs. With $a,b,r$ denoting their most significant bits,

In eight bits, $255+1$ gives R=0, C=1, V=0: signed $-1+1=0$ is in range. Conversely, $127+1$ gives R=0x80, C=0, V=1. Unsigned 128 fits, but it exceeds signed maximum 127. Combining C and V loses this distinction.

For subtraction, invert^{iInversion The NOT operation, which changes 0 to 1 and 1 to 0. A bar over an expression applies NOT to the entire expression beneath it. Learn more} only the W-bit B, then extend it with a leading 0: $T=\{0,A\}+\{0,\neg B\}+1$. Inverting all W+1 bits changes the meaning of the final carry. This lesson defines C=1 as no borrow, so unsigned $A<B$ is $\neg C$.

Signed subtraction can overflow only when the operand signs differ. A compare operation can use SUB flags without storing R. Signed $A<B$ is $N\oplus V$; signed $A\le B$ is $Z\lor(N\oplus V)$. For example, $-128-1$ is stored as +127, but V=1 corrects the error that using N alone would make.

The eight-bit ADD example below has a representable unsigned result but an out-of-range signed result. Notice that the same sum can give C=0 and V=1.

A shared adder and explicit output rules

The RTL below assumes W≥2. Opcodes 0–4 select ADD, SUB, AND, OR and XOR. Logical operations set C,V to 0. Unused opcodes set R=0, hence Z=1, with all other flags 0. These are this ALU's interface rules, not an imitation of a particular CPU instruction set.

module alu #(parameter int W = 8) (
  input  logic [W-1:0] a, b,
  input  logic [2:0] op,
  output logic [W-1:0] y,
  output logic z, n, c, v
);
  logic sub;
  logic [W-1:0] bx;
  logic [W:0] sum;
  always_comb begin
    sub = (op == 3'd1);
    bx = b ^ {W{sub}};
    sum = {1'b0, a} + {1'b0, bx}
        + {{W{1'b0}}, sub};
    y = '0;
    c = 1'b0;
    v = 1'b0;
    case (op)
      3'd0, 3'd1: begin
        y = sum[W-1:0];
        c = sum[W];
        if (sub)
          v = (a[W-1] ^ b[W-1]) & (a[W-1] ^ y[W-1]);
        else
          v = ~(a[W-1] ^ b[W-1]) & (a[W-1] ^ y[W-1]);
      end
      3'd2: y = a & b;
      3'd3: y = a | b;
      3'd4: y = a ^ b;
      default: y = '0;
    endcase
    z = ~(|y);
    n = y[W-1];
  end
endmodule

Conditional inversion of B and an initial carry express ADD/SUB with one adder structure. Computing Z and N after the selected branch has determined y gives consistent status for logical operations too. Defaults define every output path and prevent latches^{iLatch A storage element that follows its input while its control is active and holds its value while inactive. It differs from a flip-flop, which captures only at an edge. Learn more}. There are no registers^{iRegister A circuit that stores multiple bits of state. The synchronous registers in this course store their specified inputs at a clock edge. Learn more} here, hence no clock-cycle computation latency, but physical propagation delay remains. The operation-selection MUX and zero detector must also settle within the next register's setup budget.

Pair 0, the unsigned maximum, signed extrema and values on either side of boundaries in verification. Check R against a modulo $2^W$ reference, C against an extended unsigned sum, and V against signed range overflow independently. Correct R does not guarantee correct flags.

For a real example separating negative, zero, unsigned carry and signed overflow flags, see Arm's explanation of condition flags.