State equations for a shift register

Read multiple flip-flops together

For an N-bit shift register^{iRegister A circuit that stores multiple bits of state. The synchronous registers in this course store their specified inputs at a clock edge. Learn more} that inserts new input d at bit 0, the next state is

Braces denote RTL concatenation^{iConcatenation An operation that joins bit patterns side by side. Its result width is the sum of the operand widths; it is not numerical addition. Learn more}. Every bit reads the same previous state, so d does not traverse the entire register in one edge. With enable=0, hold the whole vector; with reset, load the specified initial vector.

Each column below records a rising edge^{iRising edge The instant at which the clock changes from 0 to 1. Distinguish it from a level, which refers to the entire interval during which CLK=1. Learn more}. Inputs are pre-edge; states labeled “after” are post-update. Alignment denotes sample order, not physical propagation delay^{iPropagation delay The time from an input change until the output settles to the correct value. Logical equivalence and timing behavior are separate properties. Learn more}. Starting at q=000, apply din=1 once and 0 three times. The set bit moves q0→q1→q2, then disappears.

Advance once with din=1, then three times with din=0. Confirm 001→010→100→000. Changing the input alone does not change current q; it changes only the prediction for the next edge.

Check concatenation with an arithmetic model

Interpreted as an unsigned^{iUnsigned A rule for interpreting a bit pattern as a nonnegative integer. The n-bit range is 0 through 2^n−1 and may differ from the signed interpretation of the same bits. Learn more} vector, the same transition is

For N=3, Q=5 (101), d=1: $2\cdot5+1=11$, and $11\bmod8=3$, so the next pattern is 011. This arithmetic expression offers a differently structured reference model useful for checking the concatenation implementation.

What is being stored?

Older bits move toward the highest index, while each new bit enters the lowest index. After enough accepted inputs, the register contains “the current input and the previous N-1 inputs.” The same structure supports pattern detection, simple delay lines and serial-to-parallel conversion.

Increasing storage length does not increase the bits processed per cycle. This structure accepts one bit per valid edge. Parallel input, multibit shifts and ready/valid^{iHandshake A contract that accepts a transfer when the sender's valid and the receiver's ready are both 1 at the same edge. It also defines how data must be held while waiting. Learn more} stalls each require their own datapath and control conditions.