19 / 63 · Concept

The beginning of memory: feedback, SR and D latches

Understand bistable feedback, the forbidden SR condition and D-latch transparency.

Memory needs history

A combinational output depends on current inputs. A stored output also depends on prior state. Two cross-coupled NOR gates form an active-high SR latch^{latch A storage element that follows its input during an active enable level and holds otherwise. It differs from edge-triggered storage.}:

Q=\overline{R+\overline Q},\qquad \overline Q=\overline{S+Q}

At S=R=0, both (Q,Q̅)=(1,0) and (0,1) are stable. Feedback retains the selected state.

S	R	Settled behavior
0	0	Hold
1	0	Set Q=1
0	1	Reset Q=0
1	1	Both NOR outputs 0; forbidden in normal use

Simultaneously releasing S=R=1 does not have a guaranteed final state in the digital model. Even an output named Q̅ is not complementary under that forbidden condition. A NAND SR latch has different active polarities and a different forbidden combination.

A D latch separates data from permission

An ideal positive-level D latch follows D while E=1 and holds while E=0:

Q^{+}=\begin{cases}D & E=1\\ Q & E=0\end{cases}

The logical relationship S=ED and R=E NOT D connects this to SR behavior. It is not a recipe guaranteeing safe storage from arbitrarily delayed gates; real devices impose timing constraints.

Read CLK as the latch enable

Assume both q values start at 0. The D latch follows D while CLK=1 and holds while CLK=0. The D flip-flop captures D only on a 0→1 clock transition.

Use the left circuit: keep CLK=1 and toggle D repeatedly, then lower CLK and change D again. The right circuit introduces the next lesson’s edge-triggered flip-flop^{flip-flop A storage element that captures data at a specified clock edge and holds it until another edge. Data must satisfy setup and hold requirements. Learn more}. Both start at an assumed zero, not a guaranteed physical power-up value.

Feedback alone is insufficient: feeding an inverter back to itself requires Q=NOT Q, with no binary solution. A storage element needs stable states and valid control and timing conditions.

Further reading: MIT OpenCourseWare — Sequential Logic

Try it yourself

Starting with Q=0, apply (E,D): (0,1)→(1,1)→(1,0)→(0,0)→(0,1) to a positive-level D latch. Give Q after each step.

Read the explanation

0→1→0→0→0. The latch follows D during the two E=1 steps, then holds zero. This is ideal behavior with timing conditions satisfied.