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The beginning of memory: feedback and SR/D latches

Understand the two stable states of cross-coupling, forbidden SR inputs and the transparent interval of a D latch.

An output that present inputs alone cannot explain

Remembering a brief press of a switch after it has been released requires state. A combinational circuit's output depends only on present inputs; in a storage circuit, previous state also affects the next result.

An active-high SR latch^{Latch A storage element that follows its input while its control is active and holds its value while inactive. It differs from a flip-flop, which captures only at an edge.} made from two cross-coupled NOR gates obeys

Q=\overline{R+\overline Q},\qquad \overline Q=\overline{S+Q}

For S=R=0, both (Q,Q̅)=(1,0) and (0,1) are stable solutions. Feedback preserves the previously selected state. Even though the notation says Q̅, under the forbidden condition the actual output need not be Q's complement.

S	R	Q after settling	Meaning
0	0	Previous Q	Hold
1	0	1	Set
0	1	0	Reset
1	1	Both NOR outputs are 0	Not used in normal operation

If S=R=1 is released simultaneously, a digital truth table^{Truth table A table listing every possible input combination and its output. Changes over time are checked separately with waveforms. Learn more} cannot guarantee the final state. “Forbidden” does not mean the bit pattern cannot exist; it means the desired storage behavior is not guaranteed, so the design must avoid it. An active-low^{Active-low A convention in which a request or function is active when its signal is 0. A trailing _n is a common naming convention; the specification defines the actual behavior. Learn more} SR latch made from NAND gates has different input polarity and a different forbidden combination.

A D latch separates data from permission to update

In an ideal functional model of a proper latch, Q follows D when enable=1 and retains its previous value when enable=0.

Q^{+}=\begin{cases}D & E=1\\ Q & E=0\end{cases}

The equations $S=ED$ and $R=E\overline D$ connect this behavior to SR operation. Building a safe physical latch from arbitrary delayed gates is a separate problem; timing conditions govern data transitions and the closing of enable.

Read CLK as enable and inspect the D latch's transparent interval

Assume both q values start at 0. The D latch follows D while CLK=1 and holds while CLK=0. The D flip-flop captures D only on a 0→1 clock transition.

Read CLK as E in the left-hand latch. Keep CLK=1 and change D several times: Q keeps changing too. After lowering CLK to 0, Q holds even when D changes. We compare the right-hand flip-flop^{Flip-flop An element that captures its input at a specified clock edge and holds it until the next edge. The input must meet setup and hold requirements. Learn more} in the next lesson.

Not every feedback loop is a storage element

Connecting an inverter's^{Inversion The NOT operation, which changes 0 to 1 and 1 to 0. A bar over an expression applies NOT to the entire expression beneath it. Learn more} output to its own input does not create a valid one-bit memory. $Q=\overline Q$ has no 0/1 solution. A storage element must provide stable states, input control and timing conditions.

Further reading: MIT OpenCourseWare — Sequential Logic

Try it yourself

A positive-level D latch starts with Q=0. Apply (E,D) in the order (0,1)→(1,1)→(1,0)→(0,0)→(0,1). What is the settled Q at each step?

Read the explanation

0→1→0→0→0. During the two steps with E=1, Q follows D. The final D=1 is not stored because E=0. This calculation assumes ideal behavior with timing requirements met.