11 / 63 · Concept

Decoders, one-hot selection and valid inputs

Convert binary addresses into individual select lines and design enable, range and selection invariants.

Convert an address to a select line

An $N$ -bit decoder^{Decoder A circuit that activates the output line corresponding to a binary code. With an enable input, all outputs can be set to 0 when disabled.} maps an input address to one of up to $2^N$ outputs. With enable $e$ , output $d_i$ can be defined as

d_i=e\land(a=i)

For a 2-to-4 decoder, $d_0=e\overline a_1\overline a_0$ , $d_1=e\overline a_1a_0$ , $d_2=ea_1\overline a_0$ and $d_3=ea_1a_0$ . If enable is 0, every output is 0; if it is 1, exactly one output is 1.

With enable=1, changing address a1a0 activates exactly one of d0–d3. Also set enable to 0 and confirm that every select line turns off.

From an address to one-hot select lines

d[i] = enable AND (2 × a1 + a0 = i)

Default values complete the function

SystemVerilog
module decoder2 (
  input logic en,
  input logic [1:0] addr,
  output logic [3:0] select
);
  always_comb begin
    select = 4'b0000;
    if (en) begin
      case (addr)
        2'd0: select = 4'b0001;
        2'd1: select = 4'b0010;
        2'd2: select = 4'b0100;
        2'd3: select = 4'b1000;
        default: select = 4'b0000;
      endcase
    end
  end
endmodule

The initial default assignment covers every execution path so that the previous output is not retained. Merely naming a block always_comb does not automatically turn undefined branches into a correct circuit.

When the output count is not a power of two

Selecting ten devices requires a four-bit address, but addresses 10–15 are invalid. Specify a policy such as all outputs 0 and an error flag 1. An unused code does not automatically permit arbitrary output behavior.

Verification must check the input-to-output mapping and two conditions: multiple select lines never activate together and all select lines are off when disabled. Such invariants^{Invariant A condition that must remain true in every permitted execution. For example, the occupancy of a depth-4 FIFO must always lie between 0 and 4. Learn more} are especially important for memory write enables and bus selection. Larger decoders also increase address-signal fan-out and wiring load, motivating hierarchical decoding.

Try it yourself

Design an address decoder with ten outputs. Specify the required address width, the number of invalid inputs and the condition that must hold when en=0.

Read the explanation

The address needs $\lceil\log_2 10\rceil=4$ bits, leaving six invalid codes. When en=0, every select line must be 0 regardless of the address. For invalid addresses, one possible specification sets all outputs to 0 and reports a separate error.