30 / 63 · Concept

Counter next state and reset priority

Specify increment, hold, reset and wraparound together, and calculate the result at each edge.

Specify the function with a next-state equation first

An $N$ -bit free-running counter with synchronous reset and enable follows

C_{k+1}=\begin{cases} 0&r_k=1\\ (C_k+1)\bmod2^N&r_k=0,\ e_k=1\\ C_k&r_k=0,\ e_k=0 \end{cases}

Reset^{Reset A control that returns state to a specified initial value. Define whether it is synchronous or asynchronous and whether it has priority over other controls.} has highest priority, and enable=0 holds the value. In the visualization below, toggle enable to compare incrementing with holding the value.

Starting with q=11 below, selecting reset=1 changes only the next state to 00. Advance the clock to see when the stored value changes. Release reset and step through 00→01→10→11→00. With enable=0, check that the edge count advances while q holds.

Compare state before and after a rising edge

Synchronous reset takes priority over enable. With enable=0, hold the stored value. q=11; q_next = (q + 1) mod 4

Make a prediction table for each edge

For a two-bit counter starting at 3, with reset=1 on the first edge and reset=0 thereafter, post-edge values are 0, 1, 2, 3, 0. Even if reset rises between clock edges, a synchronous register^{Register A circuit that stores multiple bits of state. The synchronous registers in this course store their specified inputs at a clock edge. Learn more} does not become 0 before the rising edge^{Rising edge The instant at which the clock changes from 0 to 1. Distinguish it from a level, which refers to the entire interval during which CLK=1. Learn more}.

Edge	Reset just before edge	Previous C	Updated C
1	1	3	0
2	0	0	1
3	0	1	2
4	0	2	3
5	0	3	0

Each column below records one rising edge. Inputs are from just before it; states labeled “after” are from just after updating. Column alignment shows sampling order, not physical propagation delay^{Propagation delay The time from an input change until the output settles to the correct value. Logical equivalence and timing behavior are separate properties. Learn more}. Starting at 3, the first edge's reset takes priority over incrementing. The final edge wraps 3 to 0.

Reset and wraparound of a two-bit counter

View waveform data

Wave data: each character is one interval; a dot holds the previous state; p is a clock cycle.
Signal	Wave	Bus values
edge	`23452`	E0 → E1 → E2 → E3 → E4
reset	`10...`
count before	`23452`	11 → 00 → 01 → 10 → 11
count after	`23452`	00 → 01 → 10 → 11 → 00

Do not mix reset semantics

An if(rst) inside always_ff @(posedge clk) is synchronous reset. It differs from asynchronous reset, which adds a reset edge to the event list. Asynchronous-reset release has separate timing requirements such as recovery/removal; do not switch merely because it reaches 0 sooner.

For a counter producing periodic pulses, specify the state or event that generates the pulse. A pulse while the value is at its maximum differs from a one-cycle pulse after the wrap-to-zero edge, changing both the output expression and observation time.

Try it yourself

A three-bit counter contains 7. At the first edge rst=0, en=0; at the next rst=0, en=1. What are the two resulting states?

Read the explanation

The first edge holds 7; the next wraps the three-bit range to 0. Retaining 8 requires more bits or a separate saturation/error policy.