Logic hazards and the limits of equivalent expressions

A truth table contains no time

With B=C=1, this expression has F=1 for either value of A:

Physical gate outputs do not change simultaneously with inputs. As A falls from 1 to 0, AB may fall first, while the inverted^{iInversion The NOT operation, which changes 0 to 1 and 1 to 0. A bar over an expression applies NOT to the entire expression beneath it. Learn more} path $\overline A C$ rises later. There can then be an interval with both terms 0. A brief 0 on an output that should remain 1 is a static-1 hazard.

Compare delays numerically

Assume these path delays to the OR inputs. They illustrate the principle and are not process-specific values.

Both OR-input terms are 0 for about 2 ns. Whether an output pulse occurs and how wide it is also depend on the OR gate's delay and short-pulse response. Passing all eight truth-table^{iTruth table A table listing every possible input combination and its output. Changes over time are checked separately with waveforms. Learn more} combinations does not verify this transient behavior.

Each cell below is 1 ns after the A transition. AB changes at 2 ns and NOT(A)C at 4 ns. The final two rows combine inputs while omitting OR delay; they are not measured device waveforms. Check how the BC=1 path covers the gap between the other terms.

A redundant term can serve a timing purpose

Add BC, which supports the output independently of A while B=C=1:

By Boolean algebra's^{iBoolean algebra Algebra of 0, 1, AND, OR and NOT. The plus sign usually denotes OR here, whose rules differ from integer addition. Learn more} consensus theorem, the stable-input function is unchanged. BC remains 1 during the A transition and covers this single-input-transition gap. In a Karnaugh map, it corresponds to covering adjacent 1 cells with a common group.

This reasoning assumes conditions such as a single-input transition and a two-level SOP implementation. It does not solve every simultaneous-input transition, dynamic hazard in multilevel logic or analog noise problem.

A term written in RTL may not survive synthesis

The synthesizer can recognize BC as functionally redundant and remove it. Merely adding the term to source does not establish a hazard-free physical implementation. Choose a suitable structure and inspect implemented paths and timing.

In a synchronous datapath, the baseline is to satisfy setup^{iSetup The minimum time that input data must be stable before the capturing clock edge. If it is violated, the stored result is not guaranteed. Learn more} and hold^{iHold time The minimum time that input data must remain stable after the capturing clock edge. Check the context to distinguish it from ordinary value retention. Learn more} so the register^{iRegister A circuit that stores multiple bits of state. The synchronous registers in this course store their specified inputs at a clock edge. Learn more} samples after the output has settled sufficiently. Directly using a glitching combinational output as a clock, asynchronous reset or external trigger can cause more serious problems. Design with the signal's purpose and receiver behavior in mind.