Lab: verify serial-data movement and bit order

The circuit and observation conditions

At every rising edge^{iRising edge The instant at which the clock changes from 0 to 1. Distinguish it from a level, which refers to the entire interval during which CLK=1. Learn more}, the lower two bits of the previous q value shift left and din enters bit 0. Apply 1, 0, 1, 1 in sequence and compare their movement.

Before starting

Prepare a Digital Design Studio Desktop project with normal execution permission. Save each example as rtl/top.sv in a separate folder.

SystemVerilog source

module top (
    input logic clk,
    input logic rst,
    input logic din,
    output logic [2:0] q
);
    // Old q[1:0] and din are captured together at each rising edge.
    always_ff @(posedge clk)
        if (rst) q <= 3'b000;
        else q <= {q[1:0], din};
endmodule

Running the lab

In New analysis, select Two-state single-clock v1. Set Clock port to clk and period to 1000ps. With the settings below, run Preflight and Run RTL simulation, then compare results.

Input stimulus

[
  {
    "inputs": {
      "din": [
        false
      ]
    }
  },
  {
    "inputs": {
      "din": [
        true
      ]
    }
  },
  {
    "inputs": {
      "din": [
        false
      ]
    }
  },
  {
    "inputs": {
      "din": [
        true
      ]
    }
  },
  {
    "inputs": {
      "din": [
        true
      ]
    }
  }
]

Each column below records a rising edge. Inputs are pre-edge; states labeled “after” are post-update. Alignment shows sampling order, not physical propagation delay^{iPropagation delay The time from an input change until the output settles to the correct value. Logical equivalence and timing behavior are separate properties. Learn more}. The first column is the reset^{iReset A control that returns state to a specified initial value. Define whether it is synchronous or asynchronous and whether it has priority over other controls. Learn more} edge, so its din=0 does not count as stored data. Compare the next four inputs with the JSON order.

Compare results

5 cycles · q=011. The rising-edge sequence is 000 → 001 → 010 → 101 → 011.

This lab uses 0/1 single-clock RTL; it does not include #delay, initial or X/Z testbenches. A lesson-completion mark is a learning record, not an actual simulation result.

Check concatenation with an independent expression

Copying the RTL concatenation^{iConcatenation An operation that joins bit patterns side by side. Its result width is the sum of the operand widths; it is not numerical addition. Learn more} as the expected answer can reproduce the same mistake in both places. Try a reference model interpreting the state as an unsigned^{iUnsigned A rule for interpreting a bit pattern as a nonnegative integer. The n-bit range is 0 through 2^n−1 and may differ from the signed interpretation of the same bits. Learn more} integer:

After reset, inputs 1, 0, 1, 1 give $0\to1\to2\to5\to3$. Written as three-bit binary, these must match the lab waveform. The final step computes $2\cdot5+1=11$; retaining the low three bits gives 3.

With reset=0 and enable=1, select din=1,0,1,1 and advance the clock after each. q becomes 001,010,101,011. Use this step model to predict behavior, then compare actual RTL results. Enable is included so you can also test the stalls in the extension below.

Track one bit to verify direction

After reset, input 1 once and then 0 three times. The sequence is 001 → 010 → 100 → 000. The first 1 must pass through bit 0, bit 1 and bit 2, then disappear. All-zero or all-one patterns alone can hide incorrect direction.

In a three-stage register^{iRegister A circuit that stores multiple bits of state. The synchronous registers in this course store their specified inputs at a clock edge. Learn more}, a bit first captured at edge $k$ reaches the highest bit 2 after edge $k+2$. Counting from the edge at which an external transmitting register launched it uses a different starting point. State the departure and arrival points in your report.

Extension: shift only valid inputs

Suppose valid is added to the input. Holding q when valid=0 differs from a pipeline that shifts every cycle while forwarding a separate valid bit. The former advances by received-bit count; the latter by elapsed clock cycles. Do not verify both against the same expected sequence.