20 / 63 · Concept

The D flip-flop: from levels to edges

Compare latch and flip-flop update times and connect them with registers, setup and hold.

Clock high and the instant it goes high are different

A positive-level latch^{Latch A storage element that follows its input while its control is active and holds its value while inactive. It differs from a flip-flop, which captures only at an edge. Learn more} follows D throughout the CLK=1 interval. A rising-edge^{Rising edge The instant at which the clock changes from 0 to 1. Distinguish it from a level, which refers to the entire interval during which CLK=1.} D flip-flop^{Flip-flop An element that captures its input at a specified clock edge and holds it until the next edge. The input must meet setup and hold requirements.} captures D at the 0-to-1 clock transition and holds it until the next rising edge. A condition saying clk=1 does not make these behaviors equivalent.

Perform this comparison:

With CLK=0, change D to 1. Both Q outputs remain 0.
Raise CLK to 1. Both Q outputs become 1.
Keep CLK=1 and change D to 0. Only the latch's Q becomes 0.
Lower CLK to 0, then raise it to 1 again. The flip-flop's Q now captures 0 too.

Two storage elements with the same D and CLK

Assume both q values start at 0. The D latch follows D while CLK=1 and holds while CLK=0. The D flip-flop captures D only on a 0→1 clock transition.

One cycle of a sequential circuit

A flip-flop's Q passing through combinational logic to form its next D creates a state transition. If $D_k$ is the input just before the edge and $Q_{k+1}$ the stored state after it, the ideal model is

Q_{k+1}=D_k

The physical output does not change instantaneously at the edge; it changes after clock-to-Q delay. Multiple flip-flops capture their own inputs at the same edge, letting them compute next state from one another's previous state. This is the starting point for counters and shift registers^{Register A circuit that stores multiple bits of state. The synchronous registers in this course store their specified inputs at a clock edge.}.

From state to next state

Current Q: Stored state in this cycle
Combinational logic: Compute D from Q and external inputs
Next rising edge: Capture D when timing requirements are met
New Q: Next-state output after clock-to-Q delay

Setup and hold are prerequisites for sampling

D must be stable for the setup^{Setup The minimum time that input data must be stable before the capturing clock edge. If it is violated, the stored result is not guaranteed. Learn more} interval before the capture edge and the hold interval^{Hold time The minimum time that input data must remain stable after the capturing clock edge. Check the context to distinguish it from ordinary value retention. Learn more} after it. If D changes near the edge, the result is not guaranteed to be simply the old or new value; metastability can arise. The interactive model above does not simulate this analog phenomenon.

A register groups multiple flip-flops. An eight-bit width alone does not guarantee that its eight input bits form one coherent value. They also need common timing conditions and data-transfer rules.

Initial state and reset

Initializing Q to 0 in a simulation does not guarantee that hardware powers up at 0. The next lesson adds reset and enable to specify initialization and retention. Synchronous reset acts at an edge; asynchronous reset acts independently of edges, but its release timing also needs attention.

Try it yourself

While CLK=1, D changes 0→1→0, then settles to 1 just before the next rising edge. When do the latch and flip-flop outputs change? Does the flip-flop update twice at the edge?

Read the explanation

The latch follows D while CLK=1. The flip-flop ignores those intervening changes and captures the valid D=1 once at the next rising edge. For a physical circuit, include setup, hold and clock-to-Q conditions.