Real button inputs: synchronization, debouncing and one event

One button press can contain many transitions

A mechanical button's contacts can repeatedly make and break before settling. Its signal is also asynchronous to the system clock. Synchronization brings a signal into a clock domain; debouncing interprets short repeated transitions as one stable state. Two flip-flop^{iFlip-flop An element that captures its input at a specified clock edge and holds it until the next edge. The input must meet setup and hold requirements. Learn more} stages do not automatically remove bounce.

This flow assumes a single-bit button level held sufficiently long. Short pulses, coherent multibit transfers and asynchronous clocks themselves require separate designs.

The N-consecutive-samples rule

Let q be the currently accepted state, x the synchronized input, and count the number of consecutive samples differing from q. At each sample, clear count to 0 if x=q. Otherwise increment it; at the Nth consecutive opposite sample, update q=x and clear count.

For N=3 and initial q=0, each column below is a sampling instant of the synchronized input, not a physical contact-voltage trace.

Specify latency and counter width

With sample interval $T_s$, acceptance takes approximately $(N-1)T_s$ to $NT_s$, depending on transition phase; add upstream synchronization latency separately. A conservative “stable for 10 ms” requirement must account for the interval between the first and last samples when choosing N. Short transitions between samples are invisible, so matching consecutive samples does not prove the physical voltage never changed in between. Specify switch characteristics and sampling conditions together.

If count stores only 0 through N−1, its width is $\max(1,\lceil\log_2 N\rceil)$. Handle N=1 too: the first opposite sample must be accepted immediately, so the ordering of the N−1 comparison matters.

Turn one press into one event

For accepted next state q_next, $rise=\overline q\,q_{next}$. The table emits the event at the same sample that accepts the change. An implementation comparing q with a one-cycle-delayed q in a separate register^{iRegister A circuit that stores multiple bits of state. The synchronous registers in this course store their specified inputs at a clock edge. Learn more} may add latency depending on observation location, so also specify when the event is consumed.