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Digital Logic Circuits

Learning outline

Learning outline
01Digital signals and number representations
Digital signals: when voltages represent 0 and 1Concept
Number systems and fixed-width representationsConcept
02Logic gates and truth tables
Basic gates: AND, OR, NOT and BUFFERConcept
Reading NAND, NOR and inversion symbolsConcept
XOR and XNOR: equality, difference and parityConcept
Universal gates: building circuits using only NANDConcept
03From Boolean expressions to circuit design
Boolean algebra, equivalent transformations and implementation costConcept
From truth tables to expressions: minterms, maxterms, SOP and POSConcept
Karnaugh maps and the conditions for don't-caresConcept
Design lab: from a specification to a three-input majority circuitLab
04Addressing and selection circuits
Decoders, one-hot selection and valid inputsConcept
Encoders and priority: choosing one of several requestsConcept
DEMUX and decoder: routing data to a selected pathConcept
Signals and ports: a contract for width, direction and timeConcept
From a truth table to a MUX and Shannon expansionConcept
05Arithmetic circuits and comparison
Adders and carry propagationConcept
Two's complement, sign extension and overflowConcept
Comparators and boundary specificationsConcept
06Latches, flip-flops and state storage
The beginning of memory: feedback and SR/D latchesConcept
The D flip-flop: from levels to edgesConcept
Flip-flops, enable and control priorityConcept
Synchronous state transitions and the role of the clockConcept
07Implementing and verifying a MUX in RTL
Combinational selection and registered-output latencyConcept
Combinational RTL and complete assignmentsConcept
Lab: exhaustive MUX testing and registered-output analysisLab
Waveform sampling times and causalityConcept
MUX verification: exhaustive tests and propertiesConcept
Design check: selection equivalence and observation timingCheck
08Counters and synchronous state updates
State count, counter width and unused codesConcept
Counter next state and reset priorityConcept
Nonblocking assignments and simultaneous state updatesConcept
Lab: verify counter reset, wraparound and invariantsLab
Modulo and saturating counters, and terminal pulsesConcept
Counter debugging and minimal counterexamplesConcept
Design check: boundaries of width, priority and wraparoundCheck
09Shift registers and data flow
Vector indexing, bit order and signednessConcept
Serial inputs and frame boundariesConcept
State equations for a shift registerConcept
Widths of slices, concatenations and replicationsConcept
Lab: verify serial-data movement and bit orderLab
Distinguishing cycle latency from throughputConcept
Shift-circuit verification and data/valid alignmentConcept
Design check: latency, alignment and preserving accepted inputsCheck
10Timing, real inputs and state machines
Setup, hold and timing budgetsConcept
Logic hazards and the limits of equivalent expressionsConcept
Clock-domain boundaries and metastabilityConcept
Real button inputs: synchronization, debouncing and one eventConcept
State machines: separating state, transitions and outputsConcept
Verification plans, coverage and independent reference modelsConcept
Capstone: an overlapping 101 pattern detectorConcept
11Optional advanced study · Arithmetic datapaths
The ALU and zero, negative, carry and overflow flagsConcept
Barrel shifters and staged multiplexersConcept
Fixed-point arithmetic, rounding and saturationConcept
A multicycle unsigned shift-add multiplierConcept
12Optional advanced study · Memory and FIFOs
Synchronous memory and read/write collision contractsConcept
A two-read, one-write register file with bypassConcept
Single-clock FIFO pointers and boundary policiesConcept
FIFO and memory verification plans with an independent scoreboardConcept
13Optional advanced study · Pipelines and interfaces
Ready/valid and a one-entry elastic bufferConcept
Multiply-add pipelines and data alignmentConcept
Stallable pipelines and backpressureConcept
Register interfaces and the timing of side effectsConcept
Capstone lab: UART transmitter and frame timingConcept

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