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Check direction, reset and input order

Use a single-bit pattern to expose reversed connections.

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Learning goals

Use a single moving bit to detect direction errors
Recalculate expected state at each edge

Symmetric patterns can hide errors

With only 000 or 111, a reversed shift may be hard to see. Sending one 1 followed by zeros produces 001 → 010 → 100 and makes the direction visible.

If you see 100 → 010 → 001 instead, check where the input is concatenated. If the first value is already wrong, compare initialization, reset and displayed bit order.

Symptom	Inspect
100 appears on first data edge	din inserted at high bit?
Always 000	Reset asserted or din stays zero?
One edge offset	Reset cycle counted as data?
All stages change to din together	Old versus newly assigned values

Predict and compare one row at a time

For each row write old q, din, rst and next q. With rst=1 the next value is 000; otherwise append din to old q[1:0]. Begin diagnosis at the first row that differs.

After understanding the original lab, practice with a copy whose input order is different. Keeping the RTL unchanged lets you focus on predicting the data flow.

Coba sendiri

After reset, inputs 1, 1, 0 produce 100, 110, 011. What would you inspect?

Baca penjelasan

Inspect for reversed concatenation that inserts din into q[2]. This course expects 001, 011, 110.