Design lab: from a requirement to a three-input voter

Fix the requirement first

Design y=1 when at least two of a, b and c are 1. Assume stable binary inputs, equal weights and no memory. “Exactly two” differs from “at least two” at 111.

Each product recognizes a pair of asserted inputs. Equivalent equations do not guarantee identical physical delay.

Majority is the full-adder carry

Read cin as c and cout as y in this experiment. Sum is odd parity^{iparity Whether the number of one bits is odd or even. Parity detects an odd number of bit flips but can miss an even number. Learn more}, a different function. Test all eight rows, especially 001 and 111.

Derive the reference independently

A suitable DUT expression is (a & b) | (a & c) | (b & c). Instead of copying it into the reference, count the one bits as integers and compare with two.

// Inside a testbench with signals a, b, c and DUT output y:
for (int v = 0; v < 8; v++) begin
  {a, b, c} = v[2:0];
  #1;
  assert (y === ((int'(a) + int'(b) + int'(c)) >= 2))
    else $fatal(1, "voter mismatch at %03b", {a,b,c});
end

The casts prevent confusion about narrow arithmetic. The testbench needs an appropriate timeunit; the delay lets its combinational logic settle and does not prove a physical 1 ns timing limit.

Adding enable e changes the requirement to $y=e(ab+ac+bc)$ and expands exhaustive coverage^{icoverage A measure of which planned conditions were exercised. A high percentage alone is not proof that a design is correct. Learn more} to 16 input combinations. Check the invariant^{iinvariant A property that must hold throughout every permitted execution, such as FIFO occupancy staying between zero and its capacity. Learn more} e=0 implies y=0 independently.