Altifigence Academy
← Pembelajaran saya

Digital Logic Circuits

Daftar isi kursus

Daftar isi kursus
01Foundations of digital logic
Binary and hexadecimalKonsep
Gates and truth tablesKonsep
Boolean algebra and De Morgan’s lawsKonsep
Decoders and enable signalsKonsep
02Signals and selection
Bits, signals and portsKonsep
Specify the selection with a truth tableKonsep
The MUX and its observation registerKonsep
03Write and run the RTL
Describe a MUX with a conditional expressionKonsep
MUX simulation labPraktikum
04Interpret and check
Input changes and sampling instantsKonsep
Test the cases that reveal mistakesKonsep
MUX knowledge checkKuis
05Arithmetic circuits and state
Half adders and full addersKonsep
Signed values and overflowKonsep
Comparators and boundary conditionsKonsep
Flip-flops and clock enableKonsep
06Numbers and time
Bit width and binary valuesKonsep
Clock edges and stateKonsep
The counter and synchronous resetKonsep
07Update state and run the lab
Compute the next value from the old valueKonsep
Counter simulation labPraktikum
08Boundaries and debugging
What follows the maximum value?Konsep
Diagnose reset and counting errorsKonsep
Counter knowledge checkKuis
09Bits and data flow
Vector direction and bit indicesKonsep
Read a serial input over timeKonsep
State changes in a shift registerKonsep
10Concatenation and the lab
Slices and concatenationKonsep
Shift-register simulation labPraktikum
11Latency and debugging
Follow a bit to the outputKonsep
Check direction, reset and input orderKonsep
Shift-register knowledge checkKuis
12Connect and verify circuits
Combinational delay and timing budgetsKonsep
Design a small state machineKonsep
Verification plans and failure tracesKonsep
Capstone: serial pattern detectorKonsep

Pilihan berlaku di peramban ini. Ubah kapan saja di bagian bawah halaman.

Penyimpanan yang diperlukan

Mendukung masuk yang aman, catatan belajar dan pengaturan tampilan yang diminta, serta pilihan privasi.

Selalu aktif

Tidak ada pelacak iklan atau analitik. Pilihan disimpan 180 hari, terpisah dari masuk atau persetujuan ketentuan.