The counter and synchronous reset

How a circuit remembers its previous value

A counter is a sequential circuit that adds one at a clock edge. A two-bit count holds four values: 00, 01, 10 and 11.

always_ff @(posedge clk) updates the register at a rising clock edge. The count on the right-hand side of <= is the value before the update.

rst is a synchronous reset. Raising rst alone does not reset the value: count becomes 00 when a rising edge occurs while rst is high.

With count=11 and rst=0, what value appears after the next rising edge?