Design a small state machine

Learning goals

• Write a state transition table.
• Separate current state from next state.

State represents what the circuit must remember.

A controller that accepts a request and waits for completion can use IDLE and BUSY. In IDLE, start=1 enters BUSY; in BUSY, done=1 returns to IDLE.

Define simultaneous inputs too. Here IDLE considers only start and BUSY only done. Reset returns to IDLE.

Compute the next state, then store it at an edge.

Combinational logic computes next_state; always_ff stores state<=next_state at the clock edge. A Moore output depends only on state; a Mealy output also depends on current inputs.

Using unsynchronized signals from another clock domain is outside this example. All inputs here are assumed stable relative to the same clock.