Digital signals: when a voltage represents a bit

What this course builds toward

Work from gates to combinational circuits, storage and finite-state machines, then complete a small design. Elementary algebra is enough to begin; basic programming helps with the later RTL labs. The optional advanced chapters extend these foundations to datapaths and interfaces.

A bit is an interpretation of a voltage

Wires carry^{icarry The value carried from one addition column to the next. The final carry and signed overflow are different conditions. Learn more} continuous voltages. A receiver guarantees low at or below $V_{IL}$ and high at or above $V_{IH}$, within its allowed operating range. The interval between them has no guaranteed binary interpretation. Device data sheets, not a universal voltage rule, specify the thresholds.

For an illustrative 3.3 V interface, let $V_{IL}=0.8\,\mathrm V$ and $V_{IH}=2.0\,\mathrm V$. An input of 1.4 V is not a third logic value: it violates the assumptions of the binary model. A transition necessarily crosses this region, so observation time matters too.

Calculate the available margin

Suppose the driver guarantees $V_{OL}\le0.2\,\mathrm V$ and $V_{OH}\ge2.8\,\mathrm V$. Then

A +0.4 V disturbance on the worst-case low leaves 0.6 V at the receiver, still a valid low. These are static margins under the specified load; they do not by themselves characterize short pulses or reflections.

Logic needs a timing contract

An AND gate produces 1 for stable inputs 11, after its propagation bound. For two gates in series with bounds 2 ns and 3 ns, allow up to 5 ns after the inputs settle. Analyze each path and take the longest bound.

An unconnected input is not a driven zero. In a four-state simulator, X means unknown and Z means high impedance; neither denotes one particular physical voltage. Interactive controls in this course model stable 0/1 values.

Further reading: MIT OpenCourseWare — The Digital Abstraction

Lab · Cross a noise-margin boundary

1. Select transmit 0. The driver is fixed at its worst-case low output, 0.20 V. At +0.60 V noise, the receiver sees 0.80 V and still guarantees 0.
2. Press the right arrow once to add 10 mV. At 0.81 V the result is no longer guaranteed. That does not mean it immediately becomes 1.
3. Select transmit 1. Starting at 2.80 V, −0.80 V noise still guarantees 1; −0.81 V does not.
4. A larger disturbance can reach the opposite valid region. The receiver then sees a valid logic level, but the transmitted data has changed.

The model does not clamp out-of-range inputs into a valid region. A real device's permitted input range, clamp current and pulse behavior require its own specification; this lab does not predict device damage or transient response.