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Half adders and full adders

Compute sum and carry separately, then chain them.

La traducción aún no está disponible. Se muestra la lección original. (English)

Learning goals

  • Distinguish sum width from carry.
  • Explain how full adders can be chained.

1+1 produces a two-bit result.

A half adder computes sum=a^b and carry=a&b. Adding 1 and 1 gives binary 10, so sum=0 and carry=1.

A full adder also adds cin from the previous position. Its sum is a^b^cin and cout=(a&b)|(a&cin)|(b&cin). Carry is 1 when at least two inputs are 1.

SystemVerilog
assign sum = a ^ b ^ cin;
assign cout = (a & b) | (a & cin) | (b & cin);

Pass carry to the next bit.

In a chain, cout from bit 0 becomes cin for bit 1. Keeping the final carry when adding two N-bit inputs requires an N+1-bit result.

Make width explicit with assign total = {1'b0, a} + {1'b0, b};. A ripple-carry implementation has propagation delay; the arithmetic expression alone does not verify its speed.

Cambiar las entradas

Inténtalo tú

Find sum and cout for a=1, b=0, cin=1.

Leer la explicación

The total is 2, or binary 10: sum=0 and cout=1.

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