33 / 36 · Concept

Combinational delay and timing budgets

Distinguish functional simulation from timing verification.

Learning goals

Identify the combinational path between registers.
Keep functional correctness separate from timing closure.

Physical circuits do not compute instantly.

After a register launches a value, it takes time to pass through logic to the next register. The input must settle before the next edge by at least the setup time.

For a simplified same-clock path, Tclk must exceed clock-to-Q + maximum combinational delay + setup + margin. Real checks also require clock skew, uncertainty, wiring and process conditions.

Check both maximum and minimum delay.

Increasing the clock period can help setup but does not solve every hold problem. Hold concerns the minimum-delay behavior near the same edge.

The provided 0/1 RTL labs are functional models. Matching waveforms do not prove that a physical chip runs at that clock speed. Timing constraints and analysis results require separate verification.

Try it yourself

With clock-to-Q=0.1ns, logic=0.7ns, setup=0.1ns and margin=0.1ns, what is the simple total?

Read the explanation

The total is 1.0ns. This is an illustrative budget, not physical timing signoff or a guaranteed operating frequency.