11 / 24 · Concept
The counter and synchronous reset
Compute the next state from the previous state.
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How a circuit remembers its previous value
A counter is a sequential circuit that adds one at a clock edge. A two-bit count holds four values: 00, 01, 10 and 11.
always_ff @(posedge clk) updates the register at a rising clock edge. The count on the right-hand side of <= is the value before the update.
rst is a synchronous reset. Raising rst alone does not reset the value: count becomes 00 when a rising edge occurs while rst is high.
| Previous | rst | After rising edge |
|---|---|---|
| 11 | 1 | 00 |
| 00 | 0 | 01 |
| 01 | 0 | 10 |
| 10 | 0 | 11 |
| 11 | 0 | 00 |
Make a prediction before running
With count=11 and rst=0, what value appears after the next rising edge?
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