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Digital Logic Circuits

Learning outline

Learning outline
01Signals and selection
Bits, signals and portsConcept
Specify the selection with a truth tableConcept
The MUX and its observation registerConcept
02Write and run the RTL
Describe a MUX with a conditional expressionConcept
MUX simulation labLab
03Interpret and check
Input changes and sampling instantsConcept
Test the cases that reveal mistakesConcept
MUX knowledge checkCheck
04Numbers and time
Bit width and binary valuesConcept
Clock edges and stateConcept
The counter and synchronous resetConcept
05Update state and run the lab
Compute the next value from the old valueConcept
Counter simulation labLab
06Boundaries and debugging
What follows the maximum value?Concept
Diagnose reset and counting errorsConcept
Counter knowledge checkCheck
07Bits and data flow
Vector direction and bit indicesConcept
Read a serial input over timeConcept
State changes in a shift registerConcept
08Concatenation and the lab
Slices and concatenationConcept
Shift-register simulation labLab
09Latency and debugging
Follow a bit to the outputConcept
Check direction, reset and input orderConcept
Shift-register knowledge checkCheck

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