4 / 24 · Concept

Describe a MUX with a conditional expression

Connect the select signal and data inputs in RTL.

Learning goals

Read both branches of a conditional expression
Separate combinational and stored paths in the code

The true branch comes first

The order is condition ? value_if_true : value_if_false. Read sel ? b : a as b when sel is 1 and a when it is 0. Writing inputs in alphabetical order can accidentally reverse the selection.

assign maintains this combinational relationship. It is not a one-time software statement that runs and stops. A relevant input change causes the expression to be evaluated again.

RTL excerpt
assign y = sel ? b : a;

always_ff @(posedge clk)
    sampled_y <= y;

Keep each signal under one driver

In the example, y is driven only by assign and sampled_y only by always_ff. Adding another assignment to y in a separate block can introduce conflicting drivers.

Change one thing at a time. Compare the selection expression with the truth table, then inspect the observation register. Adding storage to hide a combinational error makes the cause harder to find.

Try it yourself

Does assign y = sel ? a : b; match this course specification?

Read the explanation

No. It chooses a when sel=1. With a=0, b=1 and sel=1 it produces 0 instead of the expected 1.