7 / 24 · Concept

Test the cases that reveal mistakes

Choose cases that reveal reversed selection and sampling errors.

Learning goals

Choose inputs that distinguish correct and incorrect circuits
Keep expected and observed values separate

Avoid tests that let mistakes pass

If a and b always match, a broken selector can appear correct. First vary sel with a=0 and b=1; then use a=1 and b=0 to check the opposite direction.

Calculate expected values before changing the input file. Rewriting expectations after seeing the result defeats the comparison. Keep the original and modified files distinguishable.

Target	Input condition	Compare
Select direction	a != b; toggle sel	y
Unselected input	Hold selected input; toggle other	y remains stable
Storage	Change sel between edges	y versus sampled_y
All combinations	8 combinations of a, b, sel	Truth table

Start with the first mismatch

Record the first mismatching instant and its input combination. If y is wrong, inspect the selection expression and wiring. If only sampled_y is wrong, check initialization and clock edges first.

Covering eight input combinations does not verify every electrical property of a chip. The goal is to explain the 0/1 selection and storage behavior of this RTL example.

Try it yourself

y matches the truth table but sampled_y appears one edge off. What should you compare first?

Read the explanation

Compare the initial sampled_y, input transition times and first rising edge before changing the selection expression.