10 / 24 · Concept

Clock edges and state

Separate input changes from register updates.

Learning goals

Distinguish rising from falling edges
Predict when a synchronous reset takes effect

An edge is an instant, not a high interval

posedge clk identifies a rising edge. The counter does not keep incrementing throughout the high interval. It updates once per rising edge in this example.

Mark the first rising edge, then number the following edges. Compare the counter with the result calculated at each edge and check that it holds its value between them.

Reset is also sampled at an edge

The example always_ff listens only to posedge clk. Setting rst high does not change count until a rising edge. At an edge with rst=1, the register stores 00 instead of incrementing.

This describes synchronous reset. A different design with asynchronous reset can respond at another time. Read the event condition rather than inferring behavior from the signal name.

Event	rst	Change in count
Between edges	0 → 1	Hold
Rising edge	1	Store 00
Falling edge	0	Hold
Next rising edge	0	Increment

Try it yourself

Does count=10 immediately become 00 if rst rises between clock edges?

Read the explanation

No. It holds 10 until the next rising edge, when it becomes 00 if rst is still high.