20 / 24 · Concept

Slices and concatenation

Trace how concatenated bits map into the new register.

Learning goals

Map each concatenated bit to its destination
Separate pre-update and post-update values

Braces concatenate rather than add

In q <= {q[1:0], din}; the braces place bits next to each other. If the slice is 01 and din=1, the new value is 011. This does not add the numeric values one and one.

Every bit on the right is read from the old q. One edge does not insert din into q[0] and then repeatedly copy that newly written value into q[1] and q[2].

RTL excerpt
always_ff @(posedge clk)
    if (rst) q <= 3'b000;
    else q <= {q[1:0], din};

New position	Source
q[2]	Old q[1]
q[1]	Old q[0]
q[0]	din at the edge

Changing the order changes the direction

{din, q[2:1]} inserts the input at the highest position. Its width matches the original expression, but its direction differs. Valid syntax does not make the two circuits equivalent.

Substitute q=101 and din=1 into both expressions. The original yields 011; the reversed expression yields 110. A single hand-worked case can reveal a direction mistake.

Try it yourself

For q=010 and din=0, what is {q[1:0], din}?

Read the explanation

Append 0 to the slice 10 to obtain 100. The old q[2] is not used.