16 / 36 · Concept

Flip-flops and clock enable

Specify the priority of reset, enable and hold.

Learning goals

Control storage using clock enable.
Give reset priority over enable.

Holding a value is part of the behavior.

A flip-flop stores a value at a clock edge. Executing q<=d only when en=1 makes q hold when en=0. This differs from gating a clock with arbitrary combinational logic.

Placing if(rst) first gives reset priority even when rst and en are both 1. With synchronous reset, rst alone does not change q without a clock edge.

RTL excerpt
always_ff @(posedge clk) begin
  if (rst) q <= 1'b0;
  else if (en) q <= d;
end

Distinguish a register hold from an incomplete combinational assignment.

A conditional non-assignment in always_ff can intentionally hold stored state. In always_comb, assign outputs on every path to avoid unintended latches.

Test reset=1/en=1, reset=0/en=0 and reset=0/en=1 separately. Your test must distinguish reset, hold and capture.

Try it yourself

With q=1, d=0, rst=0 and en=0, what is q after the next rising edge?

Read the explanation

en=0 holds the previous value, so q remains 1.