Counter simulation lab

Prepare the example

Prepare a Digital Design Studio Desktop project and the permissions to run it. Save each example in a separate folder as rtl/top.sv.

module top (
    input logic clk,
    input logic rst,
    output logic [1:0] count
);
    // Active-high synchronous reset: sampled only at the rising clock edge.
    always_ff @(posedge clk)
        if (rst) count <= 2'b00;
        else count <= count + 2'b01;
endmodule

Run the example

In New analysis, choose Two-state single-clock v1. Set Clock port to clk and the period to 1000ps. Use the values below, run Preflight, then Run RTL simulation and compare the result.

Initial register values (LSB first)

[true,true]

Reset port

rst · Active high · 1 cycle

Maximum cycles / time

5 / 5000ps

Simulation inputs

This file sets the circuit input values at each time step. Expand the filename to inspect it, or download it for your lab.

[
  {
    "inputs": {}
  },
  {
    "inputs": {}
  },
  {
    "inputs": {}
  },
  {
    "inputs": {}
  },
  {
    "inputs": {}
  }
]

These labs use two-state, single-clock RTL. Do not add #delay, initial or X/Z testbenches. Study progress does not verify a simulator run.