22 / 24 · Concept
Follow a bit to the output
Count the edges as one input bit moves through the stages.
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Learning goals
- Count the edges at which a bit reaches each stage
- Distinguish a sample count from elapsed clock periods
Track a single one
Start at q=000, send one 1 and then only zeros. The 1 reaches q[0] after the first edge, q[1] after the second and q[2] after the third. It leaves q after the fourth.
Counting the capture edge, the bit appears at q[2] on the third sample. The time from the first capture edge to the third edge is two clock periods. State the reference instant when describing latency.
| Edge | din | q after edge | Position of 1 |
|---|---|---|---|
| 1 | 1 | 001 | q[0] |
| 2 | 0 | 010 | q[1] |
| 3 | 0 | 100 | q[2] |
| 4 | 0 | 000 | Outside q |
Width determines how much recent history remains
A three-bit shift register retains the latest three samples. Moving bits does not preserve an unlimited history. Adding stages changes both the retained history and the edge at which a bit reaches the output.
This example has no enable that pauses shifting: it moves at every rising edge. With a future enable signal, distinguish clock edges from actual shifts when reasoning about latency.
Try it yourself
After the original 1 reaches q[2], what is q after the next edge with din=0?
Read the explanation
000. Old q[2] is excluded from the expression; the two remaining zeros and the new zero fill the register.