Shift-register simulation lab

What you will learn

At each rising edge, the previous two low bits of q move left and din enters bit 0. Feed 1, 0, 1, 1 and compare each step.

Before you begin

Prepare a Digital Design Studio Desktop project and the permissions to run it. Save each example in a separate folder as rtl/top.sv.

SystemVerilog source

module top (
    input logic clk,
    input logic rst,
    input logic din,
    output logic [2:0] q
);
    // Old q[1:0] and din are captured together at each rising edge.
    always_ff @(posedge clk)
        if (rst) q <= 3'b000;
        else q <= {q[1:0], din};
endmodule

Run the example

In New analysis, choose Two-state single-clock v1. Set Clock port to clk and the period to 1000ps. Use the values below, run Preflight, then Run RTL simulation and compare the result.

Input stimulus

[
  {
    "inputs": {
      "din": [
        false
      ]
    }
  },
  {
    "inputs": {
      "din": [
        true
      ]
    }
  },
  {
    "inputs": {
      "din": [
        false
      ]
    }
  },
  {
    "inputs": {
      "din": [
        true
      ]
    }
  },
  {
    "inputs": {
      "din": [
        true
      ]
    }
  }
]

Compare the result

5 cycles · q=011. The rising-edge sequence is 000 → 001 → 010 → 101 → 011.

These labs use two-state, single-clock RTL. Do not add #delay, initial or X/Z testbenches. Study progress does not verify a simulator run.