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Input changes and sampling instants
Track y and sampled_y before and after a clock edge.
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Learning goals
- Record values on both sides of an edge
- Distinguish combinational changes from sampling delay
Write the time beside each value
Suppose a=0, b=1 and sel=0 have already been sampled. If sel changes to 1 between edges, y reflects 1 while sampled_y keeps the stored 0. After the next rising edge both are 1.
Real hardware has propagation delays and timing constraints. This table predicts selection and storage in the 0/1 RTL model; it is not a measurement of physical delay.
| Moment | sel | y | sampled_y |
|---|---|---|---|
| After earlier edge | 0 | 0 | 0 |
| Between edges | 1 | 1 | 0 |
| After next rising edge | 1 | 1 | 1 |
Trace one signal at a time
Find the sel transition and identify the selected input. Check y, then compare sampled_y after the next rising edge. Matching final values alone does not prove the intermediate behavior is correct.
Changing an input at exactly the clock edge can make event ordering confusing. For this exercise, change inputs between edges so the sampled value is unambiguous.
Experimente
If sel goes 0 → 1 → 0 between two rising edges, must sampled_y capture the intermediate 1?
Ler a explicação
No. Storage occurs at a rising edge. The intermediate change may appear on y but is not retained by sampled_y if it disappears before the edge.