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D flip-flops: from levels to edges

Compare sampling rules and connect flip-flops to registers, setup and hold.

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A level and an edge are different events

A positive-level latch^{latch A storage element that follows its input during an active enable level and holds otherwise. It differs from edge-triggered storage. Learn more} follows D throughout CLK=1. A rising-edge D flip-flop^{flip-flop A storage element that captures data at a specified clock edge and holds it until another edge. Data must satisfy setup and hold requirements.} samples D at the 0→1 transition and holds it until the next rising edge^{rising edge The transition of a clock from 0 to 1, as distinct from the entire interval during which the clock is high.}.

Try this sequence: set D=1 with CLK=0; raise CLK; change D to zero while CLK stays high; lower CLK and raise it again. The latch changes during the high level, while the flip-flop waits for the second rising edge.

Same inputs, different sampling rules

Assume both q values start at 0. The D latch follows D while CLK=1 and holds while CLK=0. The D flip-flop captures D only on a 0→1 clock transition.

One sequential cycle

Let $D_k$ be the valid input just before an edge and $Q_{k+1}$ the stored state after it. The ideal rule is

Q_{k+1}=D_k

Real Q changes after clock-to-Q delay. Connecting Q through combinational logic back to D makes a state transition. Multiple flip-flops on the same edge can compute next state from their previous states—the foundation of counters and shift registers.

From current to next state

Current Q: Stored state for this cycle
Combinational logic: Compute D from Q and external inputs
Next rising edge: Capture D with timing conditions satisfied
New Q: State appears after clock-to-Q delay

Setup and hold are assumptions of capture

D must remain stable for setup^{setup The minimum time data must be stable before the capture edge. Violating it removes the guarantee of correct capture. Learn more} time before the edge and hold time^{hold time The minimum time data must remain stable after the capture edge. Distinguish this timing requirement from the general act of holding a value. Learn more} after it. A near-edge transition can lead to metastability^{metastability A temporary analog condition in which a storage element has not settled to a valid 0 or 1. Synchronizers reduce propagation risk, rather than eliminating the possibility. Learn more}; the demonstration does not simulate that analog behavior. An 8-bit register groups flip-flops, but coherent transfer still requires a timing and data protocol.

Assuming Q starts at zero is different from guaranteed power-up behavior. Reset defines initialization. Synchronous reset acts at a clock edge; asynchronous reset can assert independently but also has release timing requirements. The next lesson adds reset and enable priorities.

Experimente

While CLK=1, D changes 0→1→0, then is stable at 1 before the next rising edge. When do latch and flip-flop outputs change? Does the flip-flop update twice at one edge?

Ler a explicação

The latch follows the high-level D transitions. The flip-flop ignores those intermediate changes and captures the valid D=1 once at the next rising edge, subject to setup, hold and clock-to-Q timing.