Counter simulation lab

What you will learn

Start at 3 and reset on the first rising edge. The sequence is then 0, 1, 2, 3, 0. A synchronous reset changes the value only at a clock edge.

Before you begin

Prepare a Digital Design Studio Desktop project and the permissions to run it. Save each example in a separate folder as rtl/top.sv.

SystemVerilog source

module top (
    input logic clk,
    input logic rst,
    output logic [1:0] count
);
    // Active-high synchronous reset: sampled only at the rising clock edge.
    always_ff @(posedge clk)
        if (rst) count <= 2'b00;
        else count <= count + 2'b01;
endmodule

Run the example

In New analysis, choose Two-state single-clock v1. Set Clock port to clk and the period to 1000ps. Use the values below, run Preflight, then Run RTL simulation and compare the result.

Input stimulus

[
  {
    "inputs": {}
  },
  {
    "inputs": {}
  },
  {
    "inputs": {}
  },
  {
    "inputs": {}
  },
  {
    "inputs": {}
  }
]

Compare the result

5 cycles · count=00. At 500, 1500, 2500, 3500 and 4500ps, look for 00 → 01 → 10 → 11 → 00.

These labs use two-state, single-clock RTL. Do not add #delay, initial or X/Z testbenches. Study progress does not verify a simulator run.