9 / 36 · Übung

MUX simulation lab

Compare outputs using the provided source and input files.

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What you will learn

When sel is 0, y follows a; when sel is 1, it follows b. sampled_y stores y at the rising clock edge and holds that value until the next rising edge.

Before you begin

Prepare a Digital Design Studio Desktop project and the permissions to run it. Save each example in a separate folder as rtl/top.sv.

SystemVerilog source

SystemVerilog
module top (
    input logic clk,
    input logic a,
    input logic b,
    input logic sel,
    output logic y,
    output logic sampled_y
);
    assign y = sel ? b : a;
    // Explicit observation register: y remains purely combinational.
    // The register makes this design eligible for logic-netlist-1 simulation.
    always_ff @(posedge clk) sampled_y <= y;
endmodule

Run the example

In New analysis, choose Two-state single-clock v1. Set Clock port to clk and the period to 1000ps. Use the values below, run Preflight, then Run RTL simulation and compare the result.

Setting	Value
Initial register values (LSB first)	[false]
Reset port	Leave empty
Maximum cycles / time	8 / 8000ps

Input stimulus

json
[
  {
    "inputs": {
      "a": [
        false
      ],
      "b": [
        false
      ],
      "sel": [
        false
      ]
    }
  },
  {
    "inputs": {
      "a": [
        false
      ],
      "b": [
        false
      ],
      "sel": [
        true
      ]
    }
  },
  {
    "inputs": {
      "a": [
        false
      ],
      "b": [
        true
      ],
      "sel": [
        false
      ]
    }
  },
  {
    "inputs": {
      "a": [
        false
      ],
      "b": [
        true
      ],
      "sel": [
        true
      ]
    }
  },
  {
    "inputs": {
      "a": [
        true
      ],
      "b": [
        false
      ],
      "sel": [
        false
      ]
    }
  },
  {
    "inputs": {
      "a": [
        true
      ],
      "b": [
        false
      ],
      "sel": [
        true
      ]
    }
  },
  {
    "inputs": {
      "a": [
        true
      ],
      "b": [
        true
      ],
      "sel": [
        false
      ]
    }
  },
  {
    "inputs": {
      "a": [
        true
      ],
      "b": [
        true
      ],
      "sel": [
        true
      ]
    }
  }
]

Compare the result

8 cycles · y=1 · sampled_y=1. At 3000ps, compare y=1 with sampled_y=0.

These labs use two-state, single-clock RTL. Do not add #delay, initial or X/Z testbenches. Study progress does not verify a simulator run.

Lesson files

mux-top.sv ↓mux-inputs.json ↓