Follow a bit to the output

Learning goals

• Count the edges at which a bit reaches each stage
• Distinguish a sample count from elapsed clock periods

Track a single one

Start at q=000, send one 1 and then only zeros. The 1 reaches q[0] after the first edge, q[1] after the second and q[2] after the third. It leaves q after the fourth.

Counting the capture edge, the bit appears at q[2] on the third sample. The time from the first capture edge to the third edge is two clock periods. State the reference instant when describing latency.

Width determines how much recent history remains

A three-bit shift register retains the latest three samples. Moving bits does not preserve an unlimited history. Adding stages changes both the retained history and the edge at which a bit reaches the output.

This example has no enable that pauses shifting: it moves at every rising edge. With a future enable signal, distinguish clock edges from actual shifts when reasoning about latency.