Verification plans and failure traces

Learning goals

• Define expected behavior before writing the implementation.
• Trace a failure from the first divergent instant.

Normal cases are not enough.

Test every MUX selection with distinct data, counter reset and wraparound, and a single 1 moving through a shift register. State which mistake each test can reveal.

Copying the implementation to calculate expected results can duplicate its bugs. For small circuits, use a truth table or independently calculated state table as the reference.

Start at the first mismatch and separate input from state.

Find the first divergent edge rather than scanning the entire trace. Compare the previous state, sampled input, reset priority and result width in order. If an input changes exactly at an edge, check the simulator’s sampling rules.

Record both tested behavior and untested cases. Passing a finite set of vectors does not prove every possible behavior.