47 / 63 · 概念
Real button inputs: synchronization, debounce and one event
Distinguish synchronization from bounce filtering and derive a consecutive-sample debouncer.
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One press can contain many transitions
A mechanical contact can bounce, and its transitions are asynchronous to the system clock. Synchronization and debouncingdebouncing Filtering repeated mechanical contact transitions to obtain a stable button state. This is separate from synchronizing an asynchronous input. solve different problems. A two-flop synchronizersynchronizer A circuit for safely handling a signal in the receiving clock domain. A multi-stage single-bit synchronizer is not by itself a coherent multi-bit transfer protocol. Learn more does not automatically remove contact bounce.
- Button: An asynchronous level with contact bounce
- Synchronizer: Receive a single-bit level in the clock domain
- Debouncer: Accept only a run of stable samples
- Edge detector: Emit one event for an accepted 0-to-1 transition
This pattern assumes a single-bit level held long enough to observe. Short pulses and coherent multi-bit transfers need other protocols.
Require N consecutive samples
Let q be the accepted state, x the synchronized input and count the number of consecutive samples differing from q. If x=q, clear count. Otherwise increment it; on the Nth differing sample, accept q=x and clear count.
For N=3 and initial q=0, inputs 0,1,0,1,1,1,1,0,1 produce counts 0,1,0,1,2,0,0,1,0. State changes at sample 5 only.
View waveform data
| Signal | Wave | Bus values |
|---|---|---|
| sample | 234523452 | 0 → 1 → 2 → 3 → 4 → 5 → 6 → 7 → 8 |
| x | 0101...01 | |
| q after | 0....1... | |
| rise event | 0....10.. |
Each column is a sampled synchronized input, not an analog contact waveform.
Specify latency and boundaries
For sample period , phase-dependent acceptance delay is roughly to , plus preceding synchronization delay. A conservative stable-time requirement must consider the interval between the first and last samples. Short transitions between samples can be missed: equal samples do not prove the physical input never changed. Specify switch characteristics and sampling assumptions together.
Storing counts 0 through N−1 needs bits. N=1 must accept the first differing sample. To emit an event on the acceptance sample, use . Comparing separately registered current and delayed states can shift event timing; define when the consumer observes it.
自己試試看
For N=3, initial q=0 and inputs 1,1,0,1,1,1, on which sample is the new state accepted? How many bits store counts 0…7 for N=8?
查看解說
The third sample resets the run, so one is accepted on the sixth sample. Counts 0…7 require three bits. An implementation storing the value 8 as well would need four bits.