DEMUX and decoder: route data to a selected output

A MUX gathers; a DEMUX distributes

A MUX^{imultiplexer A combinational circuit routing one of several inputs to the output. The select-to-input mapping must be specified. Learn more} selects one of several data inputs. A 1-to-4 DEMUX^{iDEMUX A circuit routing one data input to the selected output. The values on unselected outputs are also part of the specification.} routes a single data bit d to one selected output and drives the others low:

Reinterpret an enabled decoder

In the diagram, read a1 and a0 as the select address and enable as data d. Outputs d0…d3 correspond to y0…y3. The same Boolean function can have different application names.

Address 10 with d=1 asserts y2 only. With d=0, every output is zero, including the selected one. The global invariant^{iinvariant A property that must hold throughout every permitted execution, such as FIFO occupancy staying between zero and its capacity. Learn more} is one-hot^{ione-hot An encoding with exactly one bit set. If all-zero is also permitted, the condition is one-hot-or-zero. Learn more}-or-zero, not exactly one-hot.

Selection is not storage

A decoder^{idecoder A circuit activating the output corresponding to an input code. An enable can force all outputs inactive. Learn more} can distribute write_en to one of four registers. The decoder stores nothing: the chosen register^{iregister A circuit storing multiple state bits. The synchronous registers in this course capture specified inputs at clock edges. Learn more} captures data at its clock edge. Changing a combinational selection does not itself update stored state.

Check all eight combinations of d and address. Verify inactive outputs as well as the selected output. Settled-value checks do not prove freedom from address-transition glitches.