Bits, signals and ports

Learning goals

• Identify inputs and outputs in a port declaration
• Explain data signals and the selection signal

Start at the circuit boundary

Module ports connect the circuit to its surroundings. An input receives a value; an output exposes a value computed inside. a and b carry data, while sel chooses which one to use.

Here a, b and sel are each one bit. We work with values 0 and 1. A select value of 1 means choose b; it does not mean the selected data must be 1.

A declaration does not imply storage

logic declares a signal type, not a storage policy. In this example y is calculated by an assign expression; sampled_y is stored at a rising edge.

Mark each port direction and width, then find the statement that drives it. The assignments and clock conditions tell you more about the circuit than the signal names do.

input logic a, b, sel;
output logic y;
assign y = sel ? b : a;