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Diagnose reset and counting errors

Check the initial value, reset and first edge in order.

Chưa có bản dịch. Nội dung bài học gốc được hiển thị. (English)

Learning goals

Build an expected-state trace before observing results
Distinguish reset, initialization and bit-order mistakes

The first edge anchors the trace

The provided lab starts at 11 and resets at the first rising edge. After reset is released, the predicted observed sequence is 00, 01, 10, 11, 00. Assuming it began at 00 can shift your edge count.

The run settings apply reset for the first cycle in this lab. Check that mechanism before adding rst to the input JSON. Keep the source of a signal clear instead of controlling it from two places.

Symptom	First check
Never leaves 00	Reset remains asserted?
Sequence starts one value late	Initial state and first reset edge
01 and 10 appear swapped	Bit order in values and display
Stops at 11	RTL contains a hold condition?

Change one condition per comparison

Change initialization and reset duration in separate experiments. Changing both makes differences harder to explain. Keep the source, settings and expectations together for comparison.

If the output differs from your prediction, trace only as far as the first mismatch. Calculate the next value from count and rst at that edge before considering the rest of the waveform.

Tự thử

If count is 00 after every rising edge, should you change the addition first?

Đọc giải thích

First check whether rst stays high and whether clock edges occur. With reset asserted, the correct code repeatedly stores 00.