Clock edges and state

Learning goals

• Distinguish rising from falling edges
• Predict when a synchronous reset takes effect

An edge is an instant, not a high interval

posedge clk identifies a rising edge. The counter does not keep incrementing throughout the high interval. It updates once per rising edge in this example.

Mark the first rising edge, then number the following edges. Compare the counter with the result calculated at each edge and check that it holds its value between them.

Reset is also sampled at an edge

The example always_ff listens only to posedge clk. Setting rst high does not change count until a rising edge. At an edge with rst=1, the register stores 00 instead of incrementing.

This describes synchronous reset. A different design with asynchronous reset can respond at another time. Read the event condition rather than inferring behavior from the signal name.