Altifigence Academy

47 / 63 · 概念

Real button inputs: synchronization, debounce and one event

Distinguish synchronization from bounce filtering and derive a consecutive-sample debouncer.

译文尚未提供,以下显示课时原文。 (English)

One press can contain many transitions

A mechanical contact can bounce, and its transitions are asynchronous to the system clock. Synchronization and debouncingdebouncing Filtering repeated mechanical contact transitions to obtain a stable button state. This is separate from synchronizing an asynchronous input. solve different problems. A two-flop synchronizersynchronizer A circuit for safely handling a signal in the receiving clock domain. A multi-stage single-bit synchronizer is not by itself a coherent multi-bit transfer protocol. Learn more does not automatically remove contact bounce.

Separate the three jobs
  1. Button: An asynchronous level with contact bounce
  2. Synchronizer: Receive a single-bit level in the clock domain
  3. Debouncer: Accept only a run of stable samples
  4. Edge detector: Emit one event for an accepted 0-to-1 transition

This pattern assumes a single-bit level held long enough to observe. Short pulses and coherent multi-bit transfers need other protocols.

Require N consecutive samples

Let q be the accepted state, x the synchronized input and count the number of consecutive samples differing from q. If x=q, clear count. Otherwise increment it; on the Nth differing sample, accept q=x and clear count.

For N=3 and initial q=0, inputs 0,1,0,1,1,1,1,0,1 produce counts 0,1,0,1,2,0,0,1,0. State changes at sample 5 only.

N=3: accept the third consecutive opposite sample
View waveform data
Wave data: each character is one interval; a dot holds the previous state; p is a clock cycle.
SignalWaveBus values
sample2345234520 → 1 → 2 → 3 → 4 → 5 → 6 → 7 → 8
x0101...01
q after0....1...
rise event0....10..

Each column is a sampled synchronized input, not an analog contact waveform.

Specify latency and boundaries

For sample period TsT_s, phase-dependent acceptance delay is roughly (N1)Ts(N-1)T_s to NTsNT_s, plus preceding synchronization delay. A conservative stable-time requirement must consider the interval between the first and last samples. Short transitions between samples can be missed: equal samples do not prove the physical input never changed. Specify switch characteristics and sampling assumptions together.

Storing counts 0 through N−1 needs max(1,log2N)\max(1,\lceil\log_2 N\rceil) bits. N=1 must accept the first differing sample. To emit an event on the acceptance sample, use rise=qqnextrise=\overline q\,q_{next}. Comparing separately registered current and delayed states can shift event timing; define when the consumer observes it.

自己试试

For N=3, initial q=0 and inputs 1,1,0,1,1,1, on which sample is the new state accepted? How many bits store counts 0…7 for N=8?

阅读解释

The third sample resets the run, so one is accepted on the sixth sample. Counts 0…7 require three bits. An implementation storing the value 8 as well would need four bits.

你的选择适用于此浏览器,可随时在页脚更改。