Capstone: serial pattern detector

Learning goals

• Design a 101 detector using a transition table.
• Verify overlapping patterns and reset.

Keep only the relevant prefix as state.

S0 means no matching prefix, S1 means the last bit was 1, and S10 means the last two bits were 10. Receiving 1 in S10 completes 101.

Returning to S1 after detection reuses the last 1 as the start of another pattern. Thus 10101 matches at the third and fifth bits.

Finish by designing, predicting and comparing.

Register hit, storing the condition state==S10 and din==1 on each edge. Reset to state=S0 and hit=0. A match makes hit high for the cycle following the edge that samples that bit.

Test 000, 101, 10101, 11101 and a reset mid-pattern. The comparison tool is an educational transition model; it does not execute your RTL. Compare your own RTL against a separate simulation result.